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Energy Efficient and Process Tolerant Full Adder inTechnologies beyond CMOS
This paper presents 1-bit full adder cell in emerging technologies like FinFET and CNFET that operates in the moderate inversion region for energy efficiency, robustness and higher performance. The performance of the adder is improved by the optimum selection of important process parameters like oxide and fin thickness in FinFET and number of carbon nanotubes, chirality vector and pitch in CNFET. The optimized CNFET-based full adder (OP-CNFET) has higher speed, lower PDP (power-delay product) and lower power dissipation as compared to the MOSFET and FinFET full adder cells. The OP-CNFET design also offers tight spread in power, delay and PDP variability against process, voltage and temperature variations. All the evaluations have been carried out using HSPICE simulations based on 32 nm BPTM(Berkeley Predictive Technology Model).
Uploaded by ideseditor on 01/14/2013
Digital publication details: 7 pages.
Tags: mir · op-cnfet · op-finfet · pdp

Performance Analysis of Interconnect Drivers forUltralow Power Applications
ultralow power consumption requirement of low throughput applications needs to operate circuits in subthreshold region where subthreshold leakage current is used as active current for necessary computations. This paper investigates the impact of interconnect drivers on digital circuit performance in subthreshold region. In particular, we have investigates the performance of Si-MOSFET and CNFETs at 32nm deep submicron technology node. Performance Analysis is carried out for different interconnect drivers driving global interconnect. We have proposed an optimized CNFET driver which gives the significant improvement in delay and PDP over conventional CNFET in subthreshold for global and semi-global interconnect length.
Uploaded by ideseditor on 01/15/2013
Digital publication details: 6 pages.

Design and Analysis of Power and Variability AwareDigital Summing Circuit
Due to aggressive scaling and process imperfection in sub-45 nm technology node Vt (threshold voltage) shift is more pronounced causing large variations in circuit response. Therefore, this paper presents the analyses of various popular 1-bit digital summing circuits in light of PVT (process, voltage and temperature) variations to verify their functionality and robustness. The investigation is carried with ±3ó process parameters and ±10% VDD (supply voltage) variation by applying Gaussian distribution and Monte Carlo analysis at 22 nm technology node on HSPICE environment. Design guidelines are derived to select the most suitable topology for the design features required. Transmission Gate (TG)-based digital summing circuit is found to be the most robust against PVT variations.
Uploaded by ideseditor on 01/14/2013
Digital publication details: 9 pages.
Tags: cnfet · edp · ler · rdf · tg

A Novel Approach to Digital Gate Design
Designing the digital gates and circuits has been based on separating the designing levels: circuit level designing and device level designing. In this paper, we will discuss the point that the concept of contact in this distinction is a key-concept and that, by the progress of technology and advancing towards very tiny quantum devices as SET, necessity of having contact, because of its size is considered a basic obstacle; therefore, separating the design into designing the circuit level and device level should be stopped. In this paper, a method of a three level designing has been presented which is based on composing of some parts of the two former designing levels and the new ideas called “contact-less quantum device” and “macro-gate”. When the concept of “contact” is omitted, the concept of current in the wires and voltage of the nodes and according to them the KVL and KCL laws should also be omitted.
Uploaded by ideseditor on 01/14/2013
Digital publication details: 6 pages.